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November 2000
(R)
AS7C1024 AS7C31024
5V/3.3V 128Kx8 CMOS SRAM (Evolutionary Pinout)
Features
* AS7C1024 (5V version) * AS7C31024 (3.3V version) * Industrial and commercial temperatures * Organization: 131,072 words x 8 bits * High speed
- 10/12/15/20 ns address access time - 5/6/8/10 ns output enable access time
* 2.0V data retention * Easy memory expansion with CE1, CE2, OE inputs * TTL/LVTTL-compatible, three-state I/O * 32-pin JEDEC standard packages
300 mil SOJ 400 mil SOJ 8 x 20mm TSOP I 8 x 13.4 mm sTSOP I
* Low power consumption: ACTIVE
- 825 mW (c) / max @ 12 ns - 360 mW (AS7C31024) / max @ 12 ns
* ESD protection 2000 volts * Latch-up current 200 mA
* Low power consumption: STANDBY
- 55 mW (AS7C1024) / max CMOS - 36 mW (AS7C31024) / max CMOS
Logic block diagram
VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O7 512x256x8 Array (1,048,576) Sense amp
Pin arrangement
32-pin TSOP I (8 x 20mm) A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
Row decoder
I/O0 Column decoder A9 A10 A11 A12 A13 A14 A15 A16 WE OE CE1 CE2
Control circuit
Selection guide
AS7C1024-10 AS7C31024-10
Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current
Shaded areas contain advance information.
AS7C1024 AS7C31024 AS7C1024 AS7C31024
10 5 150 100 10 10
AS7C1024-12 AS7C1024-15 AS7C1024-20 AS7C31024-12 AS7C31024-15 AS7C31024-20 12 15 20 6 8 10 140 125 110 90 80 75 10 10 15 10 10 15
AS7C1024 AS7C31024
Unit ns ns mA mA mA mA
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ALLIANCE SEMICONDUCTOR
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Copyright (c)2000 Alliance Semiconductor. All rights reserved.
AS7C1024 AS7C31024
(R)
Functional description
The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/8/10 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (I SB1 or ISB2). For example, the AS7C31024 is guaranteed not to exceed 0.33mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable ( OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with V CC applied DC current into outputs (low) AS7C1024 AS7C31024 Symbol Vt1 Vt1 Vt2 PD Tstg Tbias IOUT Min -0.50 -0.50 -0.50 - -65 -55 - Max +7.0 +5.0 VCC +0.50 1.0 +150 +125 20 Unit V V V W
C C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE1 H X L L L CE2 X L H H H WE X X H H L OE X X H L X Data High Z High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)
Key: X = Don't Care, L = Low, H = High
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AS7C1024 AS7C31024
Recommended operating conditions
Parameter Supply voltage Device AS7C1024 AS7C31024 AS7C1024 Input voltage AS7C31024 commercial industrial Symbol VCC VCC VIH VIH VIL Ambient operating temperature
V min = -3.0V for pulse width less than t IL RC/2.
Min 4.5 3.0 2.2 2.0 -0.5 0 -40
Nominal 5.0 3.3 - - - - -
Max 5.5 3.6 VCC + 0.5 VCC + 0.5 0.8 70 85
Unit V V V V V
C C
TA TA
DC operating characteristics (over the operating range)
-10 Parameter Input leakage current Output leakage current Operating power supply current Sym Test conditions Device -12 -15 -20 Unit Min Max Min Max Min Max Min Max - - - - - - - - - 2.4 1 1 150 100 80 60 10 10 0.4 - - - - - - - - - - 2.4 1 1 140 90 75 50 10 10 0.4 - - - - - - - - - - 2.4 1 1 125 80 65 40 10 10 0.4 - - - - - - - - - - 2.4 1 1 110 mA 75 60 mA 35 15 mA AS7C31024 15 0.4 - V V
A A
|ILI| VCC = Max, VIN = GND to VCC |ILO| VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC AS7C1024 VCC = Max, CE1 = VIL, CE2 = VIH, f = fMax, I OUT = 0 AS7C31024 mA VCC = Max, CE1 VIH and/or AS7C1024 CE2 VIL, VIN = VIH or VIL, AS7C31024 f = fMax, IOUT = 0mA VCC = Max, CE1 VCC-0.2V VIN GND + 0.2V or VIN VCC -0.2V, f = 0 IOL = 8 mA, V CC = Min IOH = -4 mA, VCC = Min AS7C1024
ICC
ISB Standby power supply current ISB1 VOL VOH
Output voltage
Shaded areas contain advance information.
Capacitance (f = 1 MHz, T a = 25 C, VCC = NOMINAL)
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE1, CE2, WE, OE I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF
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AS7C1024 AS7C31024
(R)
Read cycle (over the operating range)
-10 Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time Output hold from address change CE1 Low to output in low Z CE2 High to output in low Z CE1 Low to output in high Z CE2 Low to output in high Z OE Low to output in low Z OE High to output in high Z Power up time Power down time Symbol tRC tAA tACE1 tACE2 tOE tOH tCLZ1 tCLZ2 tCHZ1 tCHZ2 tOLZ tOHZ tPU tPD Min 10 - - - - 2 3 3 - - 0 - 0 - Max - 10 10 10 3 - - - 3 3 - 3 - 10 12 - - - - 3 3 3 - - 0 - 0 - -12 Min Max - 12 12 12 3 - - - 3 3 - 3 - 12 15 - - - - 3 3 3 - - 0 - 0 - -15 Min Max - 15 15 15 4 - - - 4 4 - 4 - 15 20 - - - - 3 3 3 - - 0 - 0 - -20 Min Max - 20 20 20 5 - - - 5 5 - 5 - 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 4, 5, 12 4, 5, 12 4, 5, 12 4, 5, 12 4, 5 4, 5 4, 5, 12 4, 5, 12 3 3, 12 3, 12 Notes
Key to switching waveforms
Rising input Falling input Undefined / don't care
Read waveform 1 (address controlled)
tRC Address DOUT tAA Data valid tOH
Read waveform 2 (CE1, CE2, and OE controlled)
CE1 CE2 OE DOUT Current supply tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% 50% ICC ISB tOE tOLZ tOHZ tCHZ1, tCHZ2 tRC1
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AS7C1024 AS7C31024
Write cycle (over the operating range)
-10 Parameter Write cycle time Chip enable (CE1) to write end Chip enable (CE2) to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end
Shaded areas contain advance information.
-12 Min 12 10 10 10 0 8 0 6 0 - 3 Max - - - - - - - - - 5 - - - - - - - - - - 5 - 15 12 12 12 0 9 0 9 0 - 3
-15 Min Max - - - - - - - - - 5 - 20 12 12 12 0 12 0 10 0 - 3
-20 Min Max - - - - - - - - - 5 - Unit ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 12 12 12 Notes
Symbol tWC tCW1 tCW2 tAW tAS tWP tAH tDW tDH tWZ tOW
Min 10 9 9 9 0 7 0 6 0 - 3
Max
Write waveform 1 ( WE controlled)
tAW Address tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tWC tAH
Write waveform 2 (CE1 and CE2 controlled)
tAW Address tAS CE1 CE2 WE tWZ DIN D OUT tWP tDW Data valid tDH tCW1, tCW2 tWC tAH
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AS7C1024 AS7C31024
(R)
Data retention characteristics (over the operating range)
Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Input leakage current Symbol VDR ICCDR tCDR tR | ILI | VCC = 2.0V CE1 VCC-0.2V or CE2 0.2V VIN VCC-0.2V or VIN 0.2V AS7C1024 AS7C31024 Test conditions Device Min 2.0 - - 0 tRC - Max - 5 1 - - 1 Unit V mA mA ns ns A
Data retention waveform
Data retention mode VCC VCC tCDR CE1 VIH VDR VIH VDR 2.0V VCC tR
AC test conditions
- - - - 5V output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V.
Thevenin equivalent: 168W DOUT +1.728V (5V and 3.3V) +5V 480W +3.0V GND 90% 10% 2 ns 90% 10% D OUT 255W C(14) DOUT 255W +3.3V 320W C(14)
Figure A: Input pulse
GND Figure B: 5V Output load
GND Figure C: 3.3V Output load
Notes
1 2 3 4 5 6 7 8 9 10 11 12 13 14 During V CC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE1 and OE are Low and CE2 is High for read cycle. Address valid prior to or coincident with CE1 transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. 2V data retention applies to commercial temperature operating range only. C=30pF, except all high Z and low Z parameters, C=5pF.
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AS7C1024 AS7C31024
Typical DC and AC characteristics
Normalized supply current ICC, I SB vs. supply voltage VCC Normalized supply current ICC, ISB vs. ambient temperature T a Normalized ISB1 (log scale) 625 25 5 1 0.2 0.04 -55 -10 35 80 125 Ambient temperature (C) Normalized supply current ISB1 vs. ambient temperature Ta
1.4 1.2 Normalized ICC, ISB 1.0 0.8 0.6 0.4 0.2
1.4 1.2 Normalized ICC, ISB
ICC
1.0 0.8 0.6 0.4 0.2
ICC
VCC = VCC(NOMINAL)
ISB
ISB
0.0 MIN
NOMINAL Supply voltage (V) Normalized access time tAA vs. supply voltage VCC
MAX
0.0 -55
-10 35 80 125 Ambient temperature (C) Normalized access time tAA vs. ambient temperature T a
1.5 1.4 Normalized access time 1.3 1.2 1.1 1.0 0.9 0.8 MIN
1.5 1.4 Normalized access time
1.4 1.2
Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC
VCC = VCC(NOMINAL) Ta = 25 C
Ta = 25 C
1.2 1.1 1.0 0.9 0.8 -55 -10 35 80 125 Ambient temperature (C) Output sink current IOL vs. output voltage VOL
Normalized ICC
1.3
VCC = VCC(NOMINAL)
1.0 0.8 0.6 0.4 0.2 0.0 0
NOMINAL Supply voltage (V) Output source current I OH vs. output voltage VOH
MAX
25 50 75 Cycle frequency (MHz)
100
140 Output source current (mA) 120 100 80 60 40 20 0 0
140 Output sink current (mA) 120 100 80 60 40 20 0 VCC 0
35 30 Change in tAA (ns) 25 20 15 10 5 0 VCC 0
Typical access time change tAA vs. output capacitive loading
VCC = VCC (NOMINAL) Ta = 25 C
VCC = VCC(NOMINAL) Ta = 25 C
VCC = VCC (NOMINAL)
Output voltage (V)
Output voltage (V)
250 500 750 Capacitance (pF)
1000
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AS7C1024 AS7C31024
(R)
Package dimensions
D A S E1 E B
L e b A1 Seating Plane
Pin 1 c
eA
D e E1 E2 A1 b Pin 1 A2 E b e c Seating Plane B A
A A1 B b c D E E1 e eA L a S
32-pin PDIP Min Max 0.180 0.015 0.045 0.055 0.015 0.021 0.008 0.012 1.571 0.300 0.325 0.280 0.295 0.100 BSC 0.330 0.370 0.110 0.142 0 15 0.043
A A1 A2 B b c D E E1 E2 e
32-pin SOJ 300 mil 32-pin SOJ 400 mil Min Max Min Max 0.145 0.145 0.025 0.025 0.086 0.105 0.086 0.115 0.026 0.032 0.026 0.032 0.014 0.020 0.015 0.020 0.006 0.013 0.007 0.013 0.820 0.830 0.820 0.830 0.250 0.275 0.360 0.380 0.292 0.305 0.395 0.405 0.330 0.340 0.435 0.445 0.050 BSC 0.050 BSC 32-pin TSOP 8x20 Min Max - 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.10 0.21 18.20 18.60 0.50 nominal 7.80 8.20 19.80 20.20 0.50 0.70 0 5
D
Hd
c L pin 1 A2 A A1
pin 32
E
pin 16
pin 17
A A1 A2 b c D e E Hd L
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AS7C1024 AS7C31024
Ordering codes
Package \ Access time
Volt/Temp 5V commercial 5V industrial 3.3V commercial 3.3V industrial 5V commercial 5V industrial 3.3V commercial 3.3V industrial 5V commercial 5V industrial 3.3V commercial 3.3V industrial
10 ns AS7C1024-10TJC
12 ns AS7C1024-12TJC AS7C1024-12TJI AS7C31024-12TJC AS7C31024-12TJI AS7C1024-12JC AS7C1024-12JI AS7C31024-12JC AS7C31024-12JI AS7C1024-12TC AS7C1024-12TI AS7C31024-12TC AS7C31024-12TI
15 ns AS7C1024-15TJC AS7C1024-15TJI AS7C31024-15TJC AS7C31024-15TJI AS7C1024-15JC AS7C1024-15JI AS7C31024-15JC AS7C31024-15JI AS7C1024-15TC AS7C1024-15TI AS7C31024-15TC AS7C31024-15TI
20 ns AS7C1024-20TJC AS7C1024-20TJI AS7C31024-20TJC AS7C31024-20TJI AS7C1024-20JC AS7C1024-20JI AS7C31024-20JC AS7C31024-20JI AS7C1024-20TC AS7C1024-20TI AS7C31024-20TC AS7C31024-20TI
Plastic SOJ, 300 mL
NA
AS7C31024-10TJC
NA
AS7C1024-10JC
Plastic SOJ, 400 mL
NA
AS7C31024-10JC
NA NA NA NA NA
TSOP 8x20
NA: not available Shaded areas contain advance information.
Part numbering system
AS7C SRAM prefix X Blank=5V CMOS 3=3.3V CMOS 1024 Device number -XX Access time X Package: TP=PDIP 300 mil T=TSOP 8x20 J=SOJ 400 mil TJ=SOJ 300 mil X Temperature range C = Commercial, 0C to 70C I = Industrial, -40C to 85C
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